A system-on-chip (SoC) includes several transistors. Two types of variations, for example global variations and local variations, leads to leakage in the transistors and hence to leakage in the SoC. The global variations are inter-die variations and affect integrated circuit devices by causing differences in properties of circuit elements fabricated on different chips (dies), albeit from the same wafer, on different wafers, or on different batches of wafers. The local variations, which are intra-die variations, are differences in electrical properties that affect components of the integrated circuits fabricated on one die. The local variations include systematic variations and random variations. The systematic variations occur due to variation in strength of an instrument used for manufacturing the transistors. The random variations occur due to variation in number of atoms that enter a channel while formation of the channel of the transistors. It is desired to estimate the leakage of the SoC to manage and reduce the leakage, and in turn to improve power management of the SoC.
An existing technique for estimation of the leakage of the SoC includes corner based estimation technique. The manufacturing of the transistors can result in three types of transistors, for example weak transistors, normal transistors and strong transistors, due to the global variations. The corner based estimation technique includes identifying a strong leakage corner for a strong transistor of the SoC. The strong leakage corner can be defined as a process corner accounting for worst case leakage of the strong transistor. Computation of the leakage for various transistors of the SoC is then performed for the strong leakage corner. The leakages of the cells can then be summed to determine the leakage of the SoC. However, the leakage of one transistor is independent of that of another transistor and hence, computation of the leakage using the strong leakage corner leads to a pessimistic estimation. Moreover, local variations are not considered which may affect leakage of the SoC to a certain extent.
Another existing technique for estimation of the leakage of the SoC includes a statistical analysis process of the SoC. The statistical analysis process includes performing several simulations which makes the statistical analysis process computation intensive and in turn leads to wastage of resources. Hence, there is a need for a method to design a semiconductor device based on leakage current estimation that considers both local variations and global variations.